1. Field of the Invention
This invention relates to a circuit architecture for performing a trimming operation directly on an application board or, optionally, after the operation of packaging integrated electronic devices.
More particularly, the invention relates to an architecture as above, comprising at least a non-volatile memory unit having non-volatile memory elements and a means for changing the state of the memory elements, a first multifunctional input pin whereon a sequence of trimming data is received, and at least an additional access pin.
The invention relates, particularly but not exclusively, to a circuit architecture incorporated in a xe2x80x9chousekeepingxe2x80x9d integrated electronic device for a desktop computer, which circuit architecture operates to control and monitor output voltages from the secondary of a supply switch, known as Switching Power Supply.
The invention further relates to a method for performing trimming operations on the above integrated device with the purpose of enhancing its accuracy and turning on/off particular functions thereof.
2. Description of the Related Art
As it is well known in this specific technical field, today""s integrated circuits must meet ever-stricter specifications in regard to the ever-increasing number of parameters which require accurate determination and adjustment at the end of an integrated circuit manufacturing process. To achieve the required accuracy, it is necessary to make device trimming operations at the end of the manufacturing process, that is, on the application board and/or during the so called final test.
There are several methods to make trimming operations xe2x80x9cunder coverxe2x80x9d, that is when the integrated circuit has already been assembled in the corresponding protective package.
One such method is described, for example, in the European Patent Application No. 99830579.1, which has been assigned to the same assignee as the present patent application.
A second prior art solution is described in the Patent Application No. 00830059.2, which has also been assigned to the same assignee as the present patent application. In the former of the above patent applications, are described both a circuit architecture suitable for final test trimming, and its advantages compared to the better known electrical wafer sort trimming method.
The trimming method of the Application 99830579.1 uses two pins of the integrated circuit: a first pin for entering the trimming mode of the device, and the other for serially entering the data which, once permanently stored into memory elements, will allow certain basic parameters of the integrated circuit to be modified and set.
The circuit architecture comprises a serial interface which receives as input a string of data having a length depending on the number of memory elements to be programmed. The string of data contains a field for the data to be stored in the memory elements, a field for string control, and the information for selecting the simulation or the trimming operation.
Data acquisition is clocked by a fixed frequency clock signal which is generated internally in the integrated circuit, and the logic state (0, 1, or an end-of-sequence signal STOP) of each data is recognized in function of the distance separating one leading edge from the next in the data sequence. The string of data is first acquired and decoded, and is then loaded into a shift register, ready to be used for a trimming simulation or an actual trimming. All these operations are managed and coordinated by a state machine from the inside of the circuit. A major advantage of this first solution resides in that the trimming operation can be carried out at the final testing stage without additional pins, and in that the result can be simulated before the actual trimming, in order to check the effect of the bit sequence entered on the parameters to be set.
On the other hand, such solution has the following disadvantages:
the protocol is based on the use of an internal clock signal which makes this solution inapplicable to those devices lacking any internal or integrated clock generator;
once the data string is entered, the entered data simulation or the modified parameters measured, can be carried out only after having restored the device to its normal mode of operation; and
the simulation and trimming operations are reciprocally exclusive, and in order to trim a sequence of data which has been previously simulated, the whole string of data must be re-entered, which is time-consuming and impracticable with very long strings, that is in case a large number of memory elements require to be programmed.
The prior art solution set forth in the Application No. 00830059.2 exhibits the same drawbacks, to a greater or lesser extent.
An underlying technical problem has been to provide a circuit architecture for performing a trimming operation directly on an application board, or optionally after the operation of packaging integrated electronic devices, with such structural and functional features as to allow trimming operations to be performed also on devices which have no internal clocks, thereby overcoming the aforementioned drawbacks of the prior art.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
According to a preferred embodiment of the present invention, a trimming architecture comprises a special pin arranged for receiving a trimming operation timing signal, and with a volatile memory unit for storing a sequence of trimming data at the simulation phase, before the actual trimming operation is performed by a phase of programming the non-volatile memory unit.
According to a preferred embodiment of the present invention, a circuit architecture performs a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices, being of the type comprising at least one non-volatile memory unit having non-volatile memory elements and a means for modifying the state of the memory elements, a first multifunctional input pin whereon a sequence of trimming data is received, and at least one additional access pin, wherein it comprises a volatile memory unit associated with the non-volatile memory unit, a second multifunctional input pin whereon a timing signal of acquisition of the data is received, an interface between the first and second pins and the memory units in order to allow a data sequence to be stored into the volatile memory unit and the data acquisition to be timed, the access pin serving to switch the circuit architecture operation from the normal mode over to the trimming mode.
According to a preferred embodiment of the present invention, a method is provided for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices comprising at least one non-volatile memory unit having non-volatile memory elements and a means for modifying the state of the memory elements, a first multifunctional input pin whereon a sequence of trimming data is received, and at least one additional access pin, wherein the method comprises the steps of:
storing, in a volatile memory unit associated with the non-volatile memory unit, the state of the non-volatile memory at power-on or at the simulation phase, and further storing the sequence of trimming data at the programming phase;
switching a device operation from a normal mode to a trimming mode, through the at least one additional access pin;
timing the acquisition of the data sequence through a second multifunctional input pin whereon a timing signal is received; and
performing a trimming operation by modifying the state of the memory elements, following a comparison of a predetermined string of bits with the contents of the data sequence.
The features and advantages of the circuit architecture and the trimming method according to the present invention will be apparent from the following description of preferred embodiments thereof, given by way of non-limiting example with reference to the accompanying drawings.